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<a name="ARC-Options"></a>
<div class="header">
<p>
Next: <a href="ARM-Options.html#ARM-Options" accesskey="n" rel="next">ARM Options</a>, Previous: <a href="AMD-GCN-Options.html#AMD-GCN-Options" accesskey="p" rel="prev">AMD GCN Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Indices.html#Indices" title="Index" rel="index">Index</a>]</p>
</div>
<hr>
<a name="ARC-Options-1"></a>
<h4 class="subsection">3.19.4 ARC Options</h4>
<a name="index-ARC-options"></a>

<p>The following options control the architecture variant for which code
is being compiled:
</p>
<dl compact="compact">
<dd>
<a name="index-mbarrel_002dshifter"></a>
</dd>
<dt><code>-mbarrel-shifter</code></dt>
<dd><p>Generate instructions supported by barrel shifter.  This is the default
unless <samp>-mcpu=ARC601</samp> or &lsquo;<samp>-mcpu=ARCEM</samp>&rsquo; is in effect.
</p>
<a name="index-mjli_002dalways"></a>
</dd>
<dt><code>-mjli-always</code></dt>
<dd><p>Force to call a function using jli_s instruction.  This option is
valid only for ARCv2 architecture.
</p>
<a name="index-mcpu-1"></a>
</dd>
<dt><code>-mcpu=<var>cpu</var></code></dt>
<dd><p>Set architecture type, register usage, and instruction scheduling
parameters for <var>cpu</var>.  There are also shortcut alias options
available for backward compatibility and convenience.  Supported
values for <var>cpu</var> are
</p>
<dl compact="compact">
<dd><a name="index-mA6"></a>
<a name="index-mARC600"></a>
</dd>
<dt>&lsquo;<samp>arc600</samp>&rsquo;</dt>
<dd><p>Compile for ARC600.  Aliases: <samp>-mA6</samp>, <samp>-mARC600</samp>.
</p>
<a name="index-mARC601"></a>
</dd>
<dt>&lsquo;<samp>arc601</samp>&rsquo;</dt>
<dd><p>Compile for ARC601.  Alias: <samp>-mARC601</samp>.
</p>
<a name="index-mA7"></a>
<a name="index-mARC700"></a>
</dd>
<dt>&lsquo;<samp>arc700</samp>&rsquo;</dt>
<dd><p>Compile for ARC700.  Aliases: <samp>-mA7</samp>, <samp>-mARC700</samp>.
This is the default when configured with <samp>--with-cpu=arc700</samp>.
</p>
</dd>
<dt>&lsquo;<samp>arcem</samp>&rsquo;</dt>
<dd><p>Compile for ARC EM.
</p>
</dd>
<dt>&lsquo;<samp>archs</samp>&rsquo;</dt>
<dd><p>Compile for ARC HS.
</p>
</dd>
<dt>&lsquo;<samp>em</samp>&rsquo;</dt>
<dd><p>Compile for ARC EM CPU with no hardware extensions.
</p>
</dd>
<dt>&lsquo;<samp>em4</samp>&rsquo;</dt>
<dd><p>Compile for ARC EM4 CPU.
</p>
</dd>
<dt>&lsquo;<samp>em4_dmips</samp>&rsquo;</dt>
<dd><p>Compile for ARC EM4 DMIPS CPU.
</p>
</dd>
<dt>&lsquo;<samp>em4_fpus</samp>&rsquo;</dt>
<dd><p>Compile for ARC EM4 DMIPS CPU with the single-precision floating-point
extension.
</p>
</dd>
<dt>&lsquo;<samp>em4_fpuda</samp>&rsquo;</dt>
<dd><p>Compile for ARC EM4 DMIPS CPU with single-precision floating-point and
double assist instructions.
</p>
</dd>
<dt>&lsquo;<samp>hs</samp>&rsquo;</dt>
<dd><p>Compile for ARC HS CPU with no hardware extensions except the atomic
instructions.
</p>
</dd>
<dt>&lsquo;<samp>hs34</samp>&rsquo;</dt>
<dd><p>Compile for ARC HS34 CPU.
</p>
</dd>
<dt>&lsquo;<samp>hs38</samp>&rsquo;</dt>
<dd><p>Compile for ARC HS38 CPU.
</p>
</dd>
<dt>&lsquo;<samp>hs38_linux</samp>&rsquo;</dt>
<dd><p>Compile for ARC HS38 CPU with all hardware extensions on.
</p>
</dd>
<dt>&lsquo;<samp>hs4x</samp>&rsquo;</dt>
<dd><p>Compile for ARC HS4x CPU.
</p>
</dd>
<dt>&lsquo;<samp>hs4xd</samp>&rsquo;</dt>
<dd><p>Compile for ARC HS4xD CPU.
</p>
</dd>
<dt>&lsquo;<samp>hs4x_rel31</samp>&rsquo;</dt>
<dd><p>Compile for ARC HS4x CPU release 3.10a.
</p>
</dd>
<dt>&lsquo;<samp>arc600_norm</samp>&rsquo;</dt>
<dd><p>Compile for ARC 600 CPU with <code>norm</code> instructions enabled.
</p>
</dd>
<dt>&lsquo;<samp>arc600_mul32x16</samp>&rsquo;</dt>
<dd><p>Compile for ARC 600 CPU with <code>norm</code> and 32x16-bit multiply 
instructions enabled.
</p>
</dd>
<dt>&lsquo;<samp>arc600_mul64</samp>&rsquo;</dt>
<dd><p>Compile for ARC 600 CPU with <code>norm</code> and <code>mul64</code>-family 
instructions enabled.
</p>
</dd>
<dt>&lsquo;<samp>arc601_norm</samp>&rsquo;</dt>
<dd><p>Compile for ARC 601 CPU with <code>norm</code> instructions enabled.
</p>
</dd>
<dt>&lsquo;<samp>arc601_mul32x16</samp>&rsquo;</dt>
<dd><p>Compile for ARC 601 CPU with <code>norm</code> and 32x16-bit multiply
instructions enabled.
</p>
</dd>
<dt>&lsquo;<samp>arc601_mul64</samp>&rsquo;</dt>
<dd><p>Compile for ARC 601 CPU with <code>norm</code> and <code>mul64</code>-family
instructions enabled.
</p>
</dd>
<dt>&lsquo;<samp>nps400</samp>&rsquo;</dt>
<dd><p>Compile for ARC 700 on NPS400 chip.
</p>
</dd>
<dt>&lsquo;<samp>em_mini</samp>&rsquo;</dt>
<dd><p>Compile for ARC EM minimalist configuration featuring reduced register
set.
</p>
</dd>
</dl>

<a name="index-mdpfp"></a>
<a name="index-mdpfp_002dcompact"></a>
</dd>
<dt><code>-mdpfp</code></dt>
<dt><code>-mdpfp-compact</code></dt>
<dd><p>Generate double-precision FPX instructions, tuned for the compact
implementation.
</p>
<a name="index-mdpfp_002dfast"></a>
</dd>
<dt><code>-mdpfp-fast</code></dt>
<dd><p>Generate double-precision FPX instructions, tuned for the fast
implementation.
</p>
<a name="index-mno_002ddpfp_002dlrsr"></a>
</dd>
<dt><code>-mno-dpfp-lrsr</code></dt>
<dd><p>Disable <code>lr</code> and <code>sr</code> instructions from using FPX extension
aux registers.
</p>
<a name="index-mea"></a>
</dd>
<dt><code>-mea</code></dt>
<dd><p>Generate extended arithmetic instructions.  Currently only
<code>divaw</code>, <code>adds</code>, <code>subs</code>, and <code>sat16</code> are
supported.  Only valid for <samp>-mcpu=ARC700</samp>.
</p>
<a name="index-mno_002dmpy"></a>
<a name="index-mmpy"></a>
</dd>
<dt><code>-mno-mpy</code></dt>
<dd><p>Do not generate <code>mpy</code>-family instructions for ARC700.  This option is
deprecated.
</p>
<a name="index-mmul32x16"></a>
</dd>
<dt><code>-mmul32x16</code></dt>
<dd><p>Generate 32x16-bit multiply and multiply-accumulate instructions.
</p>
<a name="index-mmul64"></a>
</dd>
<dt><code>-mmul64</code></dt>
<dd><p>Generate <code>mul64</code> and <code>mulu64</code> instructions.  
Only valid for <samp>-mcpu=ARC600</samp>.
</p>
<a name="index-mnorm"></a>
</dd>
<dt><code>-mnorm</code></dt>
<dd><p>Generate <code>norm</code> instructions.  This is the default if <samp>-mcpu=ARC700</samp>
is in effect.
</p>
<a name="index-mspfp"></a>
<a name="index-mspfp_002dcompact"></a>
</dd>
<dt><code>-mspfp</code></dt>
<dt><code>-mspfp-compact</code></dt>
<dd><p>Generate single-precision FPX instructions, tuned for the compact
implementation.
</p>
<a name="index-mspfp_002dfast"></a>
</dd>
<dt><code>-mspfp-fast</code></dt>
<dd><p>Generate single-precision FPX instructions, tuned for the fast
implementation.
</p>
<a name="index-msimd"></a>
</dd>
<dt><code>-msimd</code></dt>
<dd><p>Enable generation of ARC SIMD instructions via target-specific
builtins.  Only valid for <samp>-mcpu=ARC700</samp>.
</p>
<a name="index-msoft_002dfloat"></a>
</dd>
<dt><code>-msoft-float</code></dt>
<dd><p>This option ignored; it is provided for compatibility purposes only.
Software floating-point code is emitted by default, and this default
can overridden by FPX options; <samp>-mspfp</samp>, <samp>-mspfp-compact</samp>, or
<samp>-mspfp-fast</samp> for single precision, and <samp>-mdpfp</samp>,
<samp>-mdpfp-compact</samp>, or <samp>-mdpfp-fast</samp> for double precision.
</p>
<a name="index-mswap"></a>
</dd>
<dt><code>-mswap</code></dt>
<dd><p>Generate <code>swap</code> instructions.
</p>
<a name="index-matomic"></a>
</dd>
<dt><code>-matomic</code></dt>
<dd><p>This enables use of the locked load/store conditional extension to implement
atomic memory built-in functions.  Not available for ARC 6xx or ARC
EM cores.
</p>
<a name="index-mdiv_002drem"></a>
</dd>
<dt><code>-mdiv-rem</code></dt>
<dd><p>Enable <code>div</code> and <code>rem</code> instructions for ARCv2 cores.
</p>
<a name="index-mcode_002ddensity"></a>
</dd>
<dt><code>-mcode-density</code></dt>
<dd><p>Enable code density instructions for ARC EM.  
This option is on by default for ARC HS.
</p>
<a name="index-mll64"></a>
</dd>
<dt><code>-mll64</code></dt>
<dd><p>Enable double load/store operations for ARC HS cores.
</p>
<a name="index-mtp_002dregno"></a>
</dd>
<dt><code>-mtp-regno=<var>regno</var></code></dt>
<dd><p>Specify thread pointer register number.
</p>
<a name="index-mmpy_002doption"></a>
</dd>
<dt><code>-mmpy-option=<var>multo</var></code></dt>
<dd><p>Compile ARCv2 code with a multiplier design option.  You can specify 
the option using either a string or numeric value for <var>multo</var>.  
&lsquo;<samp>wlh1</samp>&rsquo; is the default value.  The recognized values are:
</p>
<dl compact="compact">
<dt>&lsquo;<samp>0</samp>&rsquo;</dt>
<dt>&lsquo;<samp>none</samp>&rsquo;</dt>
<dd><p>No multiplier available.
</p>
</dd>
<dt>&lsquo;<samp>1</samp>&rsquo;</dt>
<dt>&lsquo;<samp>w</samp>&rsquo;</dt>
<dd><p>16x16 multiplier, fully pipelined.
The following instructions are enabled: <code>mpyw</code> and <code>mpyuw</code>.
</p>
</dd>
<dt>&lsquo;<samp>2</samp>&rsquo;</dt>
<dt>&lsquo;<samp>wlh1</samp>&rsquo;</dt>
<dd><p>32x32 multiplier, fully
pipelined (1 stage).  The following instructions are additionally
enabled: <code>mpy</code>, <code>mpyu</code>, <code>mpym</code>, <code>mpymu</code>, and <code>mpy_s</code>.
</p>
</dd>
<dt>&lsquo;<samp>3</samp>&rsquo;</dt>
<dt>&lsquo;<samp>wlh2</samp>&rsquo;</dt>
<dd><p>32x32 multiplier, fully pipelined
(2 stages).  The following instructions are additionally enabled: <code>mpy</code>,
<code>mpyu</code>, <code>mpym</code>, <code>mpymu</code>, and <code>mpy_s</code>.
</p>
</dd>
<dt>&lsquo;<samp>4</samp>&rsquo;</dt>
<dt>&lsquo;<samp>wlh3</samp>&rsquo;</dt>
<dd><p>Two 16x16 multipliers, blocking,
sequential.  The following instructions are additionally enabled: <code>mpy</code>,
<code>mpyu</code>, <code>mpym</code>, <code>mpymu</code>, and <code>mpy_s</code>.
</p>
</dd>
<dt>&lsquo;<samp>5</samp>&rsquo;</dt>
<dt>&lsquo;<samp>wlh4</samp>&rsquo;</dt>
<dd><p>One 16x16 multiplier, blocking,
sequential.  The following instructions are additionally enabled: <code>mpy</code>,
<code>mpyu</code>, <code>mpym</code>, <code>mpymu</code>, and <code>mpy_s</code>.
</p>
</dd>
<dt>&lsquo;<samp>6</samp>&rsquo;</dt>
<dt>&lsquo;<samp>wlh5</samp>&rsquo;</dt>
<dd><p>One 32x4 multiplier, blocking,
sequential.  The following instructions are additionally enabled: <code>mpy</code>,
<code>mpyu</code>, <code>mpym</code>, <code>mpymu</code>, and <code>mpy_s</code>.
</p>
</dd>
<dt>&lsquo;<samp>7</samp>&rsquo;</dt>
<dt>&lsquo;<samp>plus_dmpy</samp>&rsquo;</dt>
<dd><p>ARC HS SIMD support.
</p>
</dd>
<dt>&lsquo;<samp>8</samp>&rsquo;</dt>
<dt>&lsquo;<samp>plus_macd</samp>&rsquo;</dt>
<dd><p>ARC HS SIMD support.
</p>
</dd>
<dt>&lsquo;<samp>9</samp>&rsquo;</dt>
<dt>&lsquo;<samp>plus_qmacw</samp>&rsquo;</dt>
<dd><p>ARC HS SIMD support.
</p>
</dd>
</dl>

<p>This option is only available for ARCv2 cores.
</p>
<a name="index-mfpu"></a>
</dd>
<dt><code>-mfpu=<var>fpu</var></code></dt>
<dd><p>Enables support for specific floating-point hardware extensions for ARCv2
cores.  Supported values for <var>fpu</var> are:
</p>
<dl compact="compact">
<dt>&lsquo;<samp>fpus</samp>&rsquo;</dt>
<dd><p>Enables support for single-precision floating-point hardware
extensions.
</p>
</dd>
<dt>&lsquo;<samp>fpud</samp>&rsquo;</dt>
<dd><p>Enables support for double-precision floating-point hardware
extensions.  The single-precision floating-point extension is also
enabled.  Not available for ARC EM.
</p>
</dd>
<dt>&lsquo;<samp>fpuda</samp>&rsquo;</dt>
<dd><p>Enables support for double-precision floating-point hardware
extensions using double-precision assist instructions.  The single-precision
floating-point extension is also enabled.  This option is
only available for ARC EM.
</p>
</dd>
<dt>&lsquo;<samp>fpuda_div</samp>&rsquo;</dt>
<dd><p>Enables support for double-precision floating-point hardware
extensions using double-precision assist instructions.
The single-precision floating-point, square-root, and divide 
extensions are also enabled.  This option is
only available for ARC EM.
</p>
</dd>
<dt>&lsquo;<samp>fpuda_fma</samp>&rsquo;</dt>
<dd><p>Enables support for double-precision floating-point hardware
extensions using double-precision assist instructions.
The single-precision floating-point and fused multiply and add 
hardware extensions are also enabled.  This option is
only available for ARC EM.
</p>
</dd>
<dt>&lsquo;<samp>fpuda_all</samp>&rsquo;</dt>
<dd><p>Enables support for double-precision floating-point hardware
extensions using double-precision assist instructions.
All single-precision floating-point hardware extensions are also
enabled.  This option is only available for ARC EM.
</p>
</dd>
<dt>&lsquo;<samp>fpus_div</samp>&rsquo;</dt>
<dd><p>Enables support for single-precision floating-point, square-root and divide 
hardware extensions.
</p>
</dd>
<dt>&lsquo;<samp>fpud_div</samp>&rsquo;</dt>
<dd><p>Enables support for double-precision floating-point, square-root and divide 
hardware extensions.  This option
includes option &lsquo;<samp>fpus_div</samp>&rsquo;. Not available for ARC EM.
</p>
</dd>
<dt>&lsquo;<samp>fpus_fma</samp>&rsquo;</dt>
<dd><p>Enables support for single-precision floating-point and 
fused multiply and add hardware extensions.
</p>
</dd>
<dt>&lsquo;<samp>fpud_fma</samp>&rsquo;</dt>
<dd><p>Enables support for double-precision floating-point and 
fused multiply and add hardware extensions.  This option
includes option &lsquo;<samp>fpus_fma</samp>&rsquo;.  Not available for ARC EM.
</p>
</dd>
<dt>&lsquo;<samp>fpus_all</samp>&rsquo;</dt>
<dd><p>Enables support for all single-precision floating-point hardware
extensions.
</p>
</dd>
<dt>&lsquo;<samp>fpud_all</samp>&rsquo;</dt>
<dd><p>Enables support for all single- and double-precision floating-point
hardware extensions.  Not available for ARC EM.
</p>
</dd>
</dl>

<a name="index-mirq_002dctrl_002dsaved"></a>
</dd>
<dt><code>-mirq-ctrl-saved=<var>register-range</var>, <var>blink</var>, <var>lp_count</var></code></dt>
<dd><p>Specifies general-purposes registers that the processor automatically
saves/restores on interrupt entry and exit.  <var>register-range</var> is
specified as two registers separated by a dash.  The register range
always starts with <code>r0</code>, the upper limit is <code>fp</code> register.
<var>blink</var> and <var>lp_count</var> are optional.  This option is only
valid for ARC EM and ARC HS cores.
</p>
<a name="index-mrgf_002dbanked_002dregs"></a>
</dd>
<dt><code>-mrgf-banked-regs=<var>number</var></code></dt>
<dd><p>Specifies the number of registers replicated in second register bank
on entry to fast interrupt.  Fast interrupts are interrupts with the
highest priority level P0.  These interrupts save only PC and STATUS32
registers to avoid memory transactions during interrupt entry and exit
sequences.  Use this option when you are using fast interrupts in an
ARC V2 family processor.  Permitted values are 4, 8, 16, and 32.
</p>
<a name="index-mlpc_002dwidth"></a>
</dd>
<dt><code>-mlpc-width=<var>width</var></code></dt>
<dd><p>Specify the width of the <code>lp_count</code> register.  Valid values for
<var>width</var> are 8, 16, 20, 24, 28 and 32 bits.  The default width is
fixed to 32 bits.  If the width is less than 32, the compiler does not
attempt to transform loops in your program to use the zero-delay loop
mechanism unless it is known that the <code>lp_count</code> register can
hold the required loop-counter value.  Depending on the width
specified, the compiler and run-time library might continue to use the
loop mechanism for various needs.  This option defines macro
<code>__ARC_LPC_WIDTH__</code> with the value of <var>width</var>.
</p>
<a name="index-mrf16"></a>
</dd>
<dt><code>-mrf16</code></dt>
<dd><p>This option instructs the compiler to generate code for a 16-entry
register file.  This option defines the <code>__ARC_RF16__</code>
preprocessor macro.
</p>
<a name="index-mbranch_002dindex"></a>
</dd>
<dt><code>-mbranch-index</code></dt>
<dd><p>Enable use of <code>bi</code> or <code>bih</code> instructions to implement jump
tables.
</p>
</dd>
</dl>

<p>The following options are passed through to the assembler, and also
define preprocessor macro symbols.
</p>
<dl compact="compact">
<dd><a name="index-mdsp_002dpacka"></a>
</dd>
<dt><code>-mdsp-packa</code></dt>
<dd><p>Passed down to the assembler to enable the DSP Pack A extensions.
Also sets the preprocessor symbol <code>__Xdsp_packa</code>.  This option is
deprecated.
</p>
<a name="index-mdvbf"></a>
</dd>
<dt><code>-mdvbf</code></dt>
<dd><p>Passed down to the assembler to enable the dual Viterbi butterfly
extension.  Also sets the preprocessor symbol <code>__Xdvbf</code>.  This
option is deprecated.
</p>
<a name="index-mlock"></a>
</dd>
<dt><code>-mlock</code></dt>
<dd><p>Passed down to the assembler to enable the locked load/store
conditional extension.  Also sets the preprocessor symbol
<code>__Xlock</code>.
</p>
<a name="index-mmac_002dd16"></a>
</dd>
<dt><code>-mmac-d16</code></dt>
<dd><p>Passed down to the assembler.  Also sets the preprocessor symbol
<code>__Xxmac_d16</code>.  This option is deprecated.
</p>
<a name="index-mmac_002d24"></a>
</dd>
<dt><code>-mmac-24</code></dt>
<dd><p>Passed down to the assembler.  Also sets the preprocessor symbol
<code>__Xxmac_24</code>.  This option is deprecated.
</p>
<a name="index-mrtsc"></a>
</dd>
<dt><code>-mrtsc</code></dt>
<dd><p>Passed down to the assembler to enable the 64-bit time-stamp counter
extension instruction.  Also sets the preprocessor symbol
<code>__Xrtsc</code>.  This option is deprecated.
</p>
<a name="index-mswape"></a>
</dd>
<dt><code>-mswape</code></dt>
<dd><p>Passed down to the assembler to enable the swap byte ordering
extension instruction.  Also sets the preprocessor symbol
<code>__Xswape</code>.
</p>
<a name="index-mtelephony"></a>
</dd>
<dt><code>-mtelephony</code></dt>
<dd><p>Passed down to the assembler to enable dual- and single-operand
instructions for telephony.  Also sets the preprocessor symbol
<code>__Xtelephony</code>.  This option is deprecated.
</p>
<a name="index-mxy"></a>
</dd>
<dt><code>-mxy</code></dt>
<dd><p>Passed down to the assembler to enable the XY memory extension.  Also
sets the preprocessor symbol <code>__Xxy</code>.
</p>
</dd>
</dl>

<p>The following options control how the assembly code is annotated:
</p>
<dl compact="compact">
<dd><a name="index-misize"></a>
</dd>
<dt><code>-misize</code></dt>
<dd><p>Annotate assembler instructions with estimated addresses.
</p>
<a name="index-mannotate_002dalign"></a>
</dd>
<dt><code>-mannotate-align</code></dt>
<dd><p>Explain what alignment considerations lead to the decision to make an
instruction short or long.
</p>
</dd>
</dl>

<p>The following options are passed through to the linker:
</p>
<dl compact="compact">
<dd><a name="index-marclinux"></a>
</dd>
<dt><code>-marclinux</code></dt>
<dd><p>Passed through to the linker, to specify use of the <code>arclinux</code> emulation.
This option is enabled by default in tool chains built for
<code><span class="nolinebreak">arc-linux-uclibc</span></code><!-- /@w --> and <code><span class="nolinebreak">arceb-linux-uclibc</span></code><!-- /@w --> targets
when profiling is not requested.
</p>
<a name="index-marclinux_005fprof"></a>
</dd>
<dt><code>-marclinux_prof</code></dt>
<dd><p>Passed through to the linker, to specify use of the
<code>arclinux_prof</code> emulation.  This option is enabled by default in
tool chains built for <code><span class="nolinebreak">arc-linux-uclibc</span></code><!-- /@w --> and
<code><span class="nolinebreak">arceb-linux-uclibc</span></code><!-- /@w --> targets when profiling is requested.
</p>
</dd>
</dl>

<p>The following options control the semantics of generated code:
</p>
<dl compact="compact">
<dd><a name="index-mlong_002dcalls-1"></a>
</dd>
<dt><code>-mlong-calls</code></dt>
<dd><p>Generate calls as register indirect calls, thus providing access
to the full 32-bit address range.
</p>
<a name="index-mmedium_002dcalls"></a>
</dd>
<dt><code>-mmedium-calls</code></dt>
<dd><p>Don&rsquo;t use less than 25-bit addressing range for calls, which is the
offset available for an unconditional branch-and-link
instruction.  Conditional execution of function calls is suppressed, to
allow use of the 25-bit range, rather than the 21-bit range with
conditional branch-and-link.  This is the default for tool chains built
for <code><span class="nolinebreak">arc-linux-uclibc</span></code><!-- /@w --> and <code><span class="nolinebreak">arceb-linux-uclibc</span></code><!-- /@w --> targets.
</p>
<a name="index-G"></a>
</dd>
<dt><code>-G <var>num</var></code></dt>
<dd><p>Put definitions of externally-visible data in a small data section if
that data is no bigger than <var>num</var> bytes.  The default value of
<var>num</var> is 4 for any ARC configuration, or 8 when we have double
load/store operations.
</p>
<a name="index-mno_002dsdata"></a>
<a name="index-msdata"></a>
</dd>
<dt><code>-mno-sdata</code></dt>
<dd><p>Do not generate sdata references.  This is the default for tool chains
built for <code><span class="nolinebreak">arc-linux-uclibc</span></code><!-- /@w --> and <code><span class="nolinebreak">arceb-linux-uclibc</span></code><!-- /@w -->
targets.
</p>
<a name="index-mvolatile_002dcache"></a>
</dd>
<dt><code>-mvolatile-cache</code></dt>
<dd><p>Use ordinarily cached memory accesses for volatile references.  This is the
default.
</p>
<a name="index-mno_002dvolatile_002dcache"></a>
<a name="index-mvolatile_002dcache-1"></a>
</dd>
<dt><code>-mno-volatile-cache</code></dt>
<dd><p>Enable cache bypass for volatile references.
</p>
</dd>
</dl>

<p>The following options fine tune code generation:
</p><dl compact="compact">
<dd><a name="index-malign_002dcall"></a>
</dd>
<dt><code>-malign-call</code></dt>
<dd><p>Does nothing.  Preserved for backward compatibility.
</p>
<a name="index-mauto_002dmodify_002dreg"></a>
</dd>
<dt><code>-mauto-modify-reg</code></dt>
<dd><p>Enable the use of pre/post modify with register displacement.
</p>
<a name="index-mbbit_002dpeephole"></a>
</dd>
<dt><code>-mbbit-peephole</code></dt>
<dd><p>Enable bbit peephole2.
</p>
<a name="index-mno_002dbrcc"></a>
</dd>
<dt><code>-mno-brcc</code></dt>
<dd><p>This option disables a target-specific pass in <samp>arc_reorg</samp> to
generate compare-and-branch (<code>br<var>cc</var></code>) instructions.  
It has no effect on
generation of these instructions driven by the combiner pass.
</p>
<a name="index-mcase_002dvector_002dpcrel"></a>
</dd>
<dt><code>-mcase-vector-pcrel</code></dt>
<dd><p>Use PC-relative switch case tables to enable case table shortening.
This is the default for <samp>-Os</samp>.
</p>
<a name="index-mcompact_002dcasesi"></a>
</dd>
<dt><code>-mcompact-casesi</code></dt>
<dd><p>Enable compact <code>casesi</code> pattern.  This is the default for <samp>-Os</samp>,
and only available for ARCv1 cores.  This option is deprecated.
</p>
<a name="index-mno_002dcond_002dexec"></a>
</dd>
<dt><code>-mno-cond-exec</code></dt>
<dd><p>Disable the ARCompact-specific pass to generate conditional 
execution instructions.
</p>
<p>Due to delay slot scheduling and interactions between operand numbers,
literal sizes, instruction lengths, and the support for conditional execution,
the target-independent pass to generate conditional execution is often lacking,
so the ARC port has kept a special pass around that tries to find more
conditional execution generation opportunities after register allocation,
branch shortening, and delay slot scheduling have been done.  This pass
generally, but not always, improves performance and code size, at the cost of
extra compilation time, which is why there is an option to switch it off.
If you have a problem with call instructions exceeding their allowable
offset range because they are conditionalized, you should consider using
<samp>-mmedium-calls</samp> instead.
</p>
<a name="index-mearly_002dcbranchsi"></a>
</dd>
<dt><code>-mearly-cbranchsi</code></dt>
<dd><p>Enable pre-reload use of the <code>cbranchsi</code> pattern.
</p>
<a name="index-mexpand_002dadddi"></a>
</dd>
<dt><code>-mexpand-adddi</code></dt>
<dd><p>Expand <code>adddi3</code> and <code>subdi3</code> at RTL generation time into
<code>add.f</code>, <code>adc</code> etc.  This option is deprecated.
</p>
<a name="index-mindexed_002dloads"></a>
</dd>
<dt><code>-mindexed-loads</code></dt>
<dd><p>Enable the use of indexed loads.  This can be problematic because some
optimizers then assume that indexed stores exist, which is not
the case.
</p>
<a name="index-mlra"></a>
</dd>
<dt><code>-mlra</code></dt>
<dd><p>Enable Local Register Allocation.  This is still experimental for ARC,
so by default the compiler uses standard reload
(i.e. <samp>-mno-lra</samp>).
</p>
<a name="index-mlra_002dpriority_002dnone"></a>
</dd>
<dt><code>-mlra-priority-none</code></dt>
<dd><p>Don&rsquo;t indicate any priority for target registers.
</p>
<a name="index-mlra_002dpriority_002dcompact"></a>
</dd>
<dt><code>-mlra-priority-compact</code></dt>
<dd><p>Indicate target register priority for r0..r3 / r12..r15.
</p>
<a name="index-mlra_002dpriority_002dnoncompact"></a>
</dd>
<dt><code>-mlra-priority-noncompact</code></dt>
<dd><p>Reduce target register priority for r0..r3 / r12..r15.
</p>
<a name="index-mmillicode"></a>
</dd>
<dt><code>-mmillicode</code></dt>
<dd><p>When optimizing for size (using <samp>-Os</samp>), prologues and epilogues
that have to save or restore a large number of registers are often
shortened by using call to a special function in libgcc; this is
referred to as a <em>millicode</em> call.  As these calls can pose
performance issues, and/or cause linking issues when linking in a
nonstandard way, this option is provided to turn on or off millicode
call generation.
</p>
<a name="index-mcode_002ddensity_002dframe"></a>
</dd>
<dt><code>-mcode-density-frame</code></dt>
<dd><p>This option enable the compiler to emit <code>enter</code> and <code>leave</code>
instructions.  These instructions are only valid for CPUs with
code-density feature.
</p>
<a name="index-mmixed_002dcode"></a>
</dd>
<dt><code>-mmixed-code</code></dt>
<dd><p>Does nothing.  Preserved for backward compatibility.
</p>
<a name="index-mq_002dclass"></a>
</dd>
<dt><code>-mq-class</code></dt>
<dd><p>Ths option is deprecated.  Enable &lsquo;<samp>q</samp>&rsquo; instruction alternatives.
This is the default for <samp>-Os</samp>.
</p>
<a name="index-mRcq"></a>
</dd>
<dt><code>-mRcq</code></dt>
<dd><p>Does nothing.  Preserved for backward compatibility.
</p>
<a name="index-mRcw"></a>
</dd>
<dt><code>-mRcw</code></dt>
<dd><p>Does nothing.  Preserved for backward compatibility.
</p>
<a name="index-msize_002dlevel"></a>
</dd>
<dt><code>-msize-level=<var>level</var></code></dt>
<dd><p>Fine-tune size optimization with regards to instruction lengths and alignment.
The recognized values for <var>level</var> are:
</p><dl compact="compact">
<dt>&lsquo;<samp>0</samp>&rsquo;</dt>
<dd><p>No size optimization.  This level is deprecated and treated like &lsquo;<samp>1</samp>&rsquo;.
</p>
</dd>
<dt>&lsquo;<samp>1</samp>&rsquo;</dt>
<dd><p>Short instructions are used opportunistically.
</p>
</dd>
<dt>&lsquo;<samp>2</samp>&rsquo;</dt>
<dd><p>In addition, alignment of loops and of code after barriers are dropped.
</p>
</dd>
<dt>&lsquo;<samp>3</samp>&rsquo;</dt>
<dd><p>In addition, optional data alignment is dropped, and the option <samp>Os</samp> is enabled.
</p>
</dd>
</dl>

<p>This defaults to &lsquo;<samp>3</samp>&rsquo; when <samp>-Os</samp> is in effect.  Otherwise,
the behavior when this is not set is equivalent to level &lsquo;<samp>1</samp>&rsquo;.
</p>
<a name="index-mtune-2"></a>
</dd>
<dt><code>-mtune=<var>cpu</var></code></dt>
<dd><p>Set instruction scheduling parameters for <var>cpu</var>, overriding any implied
by <samp>-mcpu=</samp>.
</p>
<p>Supported values for <var>cpu</var> are
</p>
<dl compact="compact">
<dt>&lsquo;<samp>ARC600</samp>&rsquo;</dt>
<dd><p>Tune for ARC600 CPU.
</p>
</dd>
<dt>&lsquo;<samp>ARC601</samp>&rsquo;</dt>
<dd><p>Tune for ARC601 CPU.
</p>
</dd>
<dt>&lsquo;<samp>ARC700</samp>&rsquo;</dt>
<dd><p>Tune for ARC700 CPU with standard multiplier block.
</p>
</dd>
<dt>&lsquo;<samp>ARC700-xmac</samp>&rsquo;</dt>
<dd><p>Tune for ARC700 CPU with XMAC block.
</p>
</dd>
<dt>&lsquo;<samp>ARC725D</samp>&rsquo;</dt>
<dd><p>Tune for ARC725D CPU.
</p>
</dd>
<dt>&lsquo;<samp>ARC750D</samp>&rsquo;</dt>
<dd><p>Tune for ARC750D CPU.
</p>
</dd>
<dt>&lsquo;<samp>core3</samp>&rsquo;</dt>
<dd><p>Tune for ARCv2 core3 type CPU.  This option enable usage of
<code>dbnz</code> instruction.
</p>
</dd>
<dt>&lsquo;<samp>release31a</samp>&rsquo;</dt>
<dd><p>Tune for ARC4x release 3.10a.
</p>
</dd>
</dl>

<a name="index-mmultcost"></a>
</dd>
<dt><code>-mmultcost=<var>num</var></code></dt>
<dd><p>Cost to assume for a multiply instruction, with &lsquo;<samp>4</samp>&rsquo; being equal to a
normal instruction.
</p>
<a name="index-munalign_002dprob_002dthreshold"></a>
</dd>
<dt><code>-munalign-prob-threshold=<var>probability</var></code></dt>
<dd><p>Does nothing.  Preserved for backward compatibility.
</p>
</dd>
</dl>

<p>The following options are maintained for backward compatibility, but
are now deprecated and will be removed in a future release:
</p>
<dl compact="compact">
<dd>
<a name="index-margonaut"></a>
</dd>
<dt><code>-margonaut</code></dt>
<dd><p>Obsolete FPX.
</p>
<a name="index-mbig_002dendian-1"></a>
<a name="index-EB"></a>
</dd>
<dt><code>-mbig-endian</code></dt>
<dt><code>-EB</code></dt>
<dd><p>Compile code for big-endian targets.  Use of these options is now
deprecated.  Big-endian code is supported by configuring GCC to build
<code><span class="nolinebreak">arceb-elf32</span></code><!-- /@w --> and <code><span class="nolinebreak">arceb-linux-uclibc</span></code><!-- /@w --> targets,
for which big endian is the default.
</p>
<a name="index-mlittle_002dendian-1"></a>
<a name="index-EL"></a>
</dd>
<dt><code>-mlittle-endian</code></dt>
<dt><code>-EL</code></dt>
<dd><p>Compile code for little-endian targets.  Use of these options is now
deprecated.  Little-endian code is supported by configuring GCC to build 
<code><span class="nolinebreak">arc-elf32</span></code><!-- /@w --> and <code><span class="nolinebreak">arc-linux-uclibc</span></code><!-- /@w --> targets,
for which little endian is the default.
</p>
<a name="index-mbarrel_005fshifter"></a>
</dd>
<dt><code>-mbarrel_shifter</code></dt>
<dd><p>Replaced by <samp>-mbarrel-shifter</samp>.
</p>
<a name="index-mdpfp_005fcompact"></a>
</dd>
<dt><code>-mdpfp_compact</code></dt>
<dd><p>Replaced by <samp>-mdpfp-compact</samp>.
</p>
<a name="index-mdpfp_005ffast"></a>
</dd>
<dt><code>-mdpfp_fast</code></dt>
<dd><p>Replaced by <samp>-mdpfp-fast</samp>.
</p>
<a name="index-mdsp_005fpacka"></a>
</dd>
<dt><code>-mdsp_packa</code></dt>
<dd><p>Replaced by <samp>-mdsp-packa</samp>.
</p>
<a name="index-mEA"></a>
</dd>
<dt><code>-mEA</code></dt>
<dd><p>Replaced by <samp>-mea</samp>.
</p>
<a name="index-mmac_005f24"></a>
</dd>
<dt><code>-mmac_24</code></dt>
<dd><p>Replaced by <samp>-mmac-24</samp>.
</p>
<a name="index-mmac_005fd16"></a>
</dd>
<dt><code>-mmac_d16</code></dt>
<dd><p>Replaced by <samp>-mmac-d16</samp>.
</p>
<a name="index-mspfp_005fcompact"></a>
</dd>
<dt><code>-mspfp_compact</code></dt>
<dd><p>Replaced by <samp>-mspfp-compact</samp>.
</p>
<a name="index-mspfp_005ffast"></a>
</dd>
<dt><code>-mspfp_fast</code></dt>
<dd><p>Replaced by <samp>-mspfp-fast</samp>.
</p>
<a name="index-mtune-3"></a>
</dd>
<dt><code>-mtune=<var>cpu</var></code></dt>
<dd><p>Values &lsquo;<samp>arc600</samp>&rsquo;, &lsquo;<samp>arc601</samp>&rsquo;, &lsquo;<samp>arc700</samp>&rsquo; and
&lsquo;<samp>arc700-xmac</samp>&rsquo; for <var>cpu</var> are replaced by &lsquo;<samp>ARC600</samp>&rsquo;,
&lsquo;<samp>ARC601</samp>&rsquo;, &lsquo;<samp>ARC700</samp>&rsquo; and &lsquo;<samp>ARC700-xmac</samp>&rsquo; respectively.
</p>
<a name="index-multcost"></a>
</dd>
<dt><code>-multcost=<var>num</var></code></dt>
<dd><p>Replaced by <samp>-mmultcost</samp>.
</p>
</dd>
</dl>

<hr>
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